1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device. More particularly, the present invention relates to a fabrication method of a landing pad.
2. Description of the Related Art
As semiconductors enter the stage of deep sub-micron processing, the device dimensions are gradually decreased. The fabrication of a landing plug is one approach to increase the aligned margin for photolithography when semiconductor devices become highly integrated.
FIGS. 1A to 1C are schematic, cross-sectional views showing the fabrication of a landing pad, which is applicable to an embedded dynamic random access memory device according to the prior art
Referring to FIG. 1A, a device isolation structure 30 is formed on the substrate 10 to define the active regions 15 and 20, wherein the active region 15 is a logic circuit region and the active region 20 is a dynamic random access memory region.
Transistors are formed on the active regions 15 and 20 respectively. Each transistor comprises a gate 40 and source/drain regions 70 in the substrate 10 at both sides of the gate 40. A silicon nitride cap layer 50 is formed on the gate 40 with silicon nitride spacers 60 formed on the sidewalls of the gate 40.
A silicon nitride layer 80 is then formed covering the active region 20. A salicide process is conducted to form a titanium silicide layer 90 on the source/drain regions 70 in the active region 15.
As shown in FIG. 1B, a silicon oxide layer 100 is formed on the active regions 15 and 20, followed by defining the silicon oxide layer 100 and the underlying silicon nitride layer 80 in the active region 20 to form an opening 110 above the source/drain region of the active region 20.
Referring to FIG. 1C, a doped polysilicon type of landing pad 120 is formed in the opening 110 and on the silicon oxide layer 100 at the periphery of the opening 110 to increase the aligned margin for photolithography performed in the subsequent formation of a contact plug. Subsequently an insulation layer (not shown) is then formed, followed by the formation a contact plug (not shown) to complete the manufacturing of an embedded DRAM device.
However, during the entire fabrication process, the wafer is being transferred between the various instruments. When the substrate 10 contacts air, the surface of the substrate 10 is oxidized to form a native oxide layer which affects the contact resistance between the source/drain region 70 and the landing pad 120. Furthermore, the resistance of the doped polysilicon landing pad 120 is higher than either a metal silicide or a metal. The RC delay time is thus greatly increased and the operating efficiency of the entire integrated circuit is adversely affected.